1. Field of the Invention
The present invention relates to a packaged semiconductor device having an LOC (lead on chip) structure in which inner leads are arranged on a semiconductor chip.
2. Description of the Related Art
A packaged semiconductor device which has an LOC structure is disclosed in, for example, Japanese Patent Publications 61-241959 and 2-246125. The internal structure of such a semiconductor apparatus is shown in FIG. 5. The LOC structure is advantageous for packaging a large chip having a large capacity or many functions in a package and for achieving good electric characteristics. Referring to FIG. 5, a large chip 101 sealed by sealing resin 110 carries in a central portion of the top surface thereof a row of bonding pads 102 arranged along the length of the semiconductor chip 101. The bonding pads 102 include signal pads, power pads, and ground pads. The power pads and the ground pads are provided to mitigate electric noise. The top surface of the semiconductor 101 except a portion where the bonding pads 102 are provided is covered by an insulating .alpha.-barrier 103 which blocks .alpha. rays.
A plurality of leads 104 are arranged on top of the .alpha.-barrier 103. The inside terminal of each lead 104 is electrically connected to a corresponding bonding pad 102 by means of Au-wire 105. Four leads 106 are provided in lengthwise end portions of the semiconductor chip 101. The leads 106 at opposite ends are connected to each other by means of buses 107 provided on the .alpha.-barrier 103. These end-portion leads 106 and buses 107 connecting them are connected to the bonding pads 102 at different sites and used as a power lead, a ground lead, and a reference-voltage lead. The buses 107 longitudinally extend beside the row of bonding pads 102 through a central portion of the semiconductor chip 101. Such buses 107 make it possible to connect the buses 107 at different locations to the power pads and/or the ground pads 102. The buses 107 also cool the semiconductor chip 101. The leads 104 and 106 also serve as die pads.
A conventional semiconductor apparatus employs a wire bonding method in which Au-wires are used to connect the bonding pads and the inside terminals of the leads. Lately, there has been a growing demand for a thin packaged semiconductor device, for example, having a thickness of 0.5 mm or less for a memory card. To produce such a thin semiconductor device, a TAB (tape automated bonding) method in which leads are directly connected to bonding pads is more advantageous than the wire bonding method. However, if the TAB method is employed in the structure of a conventional semiconductor apparatus, a problem will be caused. Because a plurality of power pads, ground pads, and signal pads are arranged in a row in the conventional structure, the power pads or the ground pads for reducing electrical noise cannot be directly connected to a single lead. Therefore, an attempt to reduce electrical noise will fail if the TAB method is employed in the conventional structure.